Process for producing semiconductor article using graded epitaxial growth

ABSTRACT

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si 1−x Ge x  (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si 1−y Ge y  layer, a thin strained Si 1−z Ge z  layer and another relaxed Si 1−y Ge y  layer. Hydrogen ions are then introduced into the strained Si z Ge z  layer. The relaxed Si 1−y Ge y  layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si 1−y Ge y  layer remains on the second substrate. In another exemplary embodiment, a graded Si 1−x Ge x  is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

PRIORITY INFORMATION

[0001] This application claims priority from provisional applicationSer. No. 60/225,666 filed Aug. 16, 2000.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a production of a generalsubstrate of relaxed Si_(1−x)Ge_(x)-on-insulator (SGOI) for variouselectronics or optoelectronics applications, and the production ofmonocrystalline III-V or II-VI material-on-insulator substrate.

[0003] Relaxed Si_(1−x)Ge_(x)-on-insulator (SGOI) is a very promisingtechnology as it combines the benefits of two advanced technologies: theconventional SOI technology and the disruptive SiGe technology. The SOIconfiguration offers various advantages associated with the insulatingsubstrate, namely reduced parasitic capacitances, improved isolation,reduced short-channel-effect, etc. High mobility strained-Si,strained-Si_(1−x)Ge_(x) or strained-Ge MOS devices can be made on SGOIsubstrates.

[0004] Other III-V optoelectronic devices can also be integrated intothe SGOI substrate by matching the lattice constants of III-V materialsand the relaxed Si_(1−x)Ge_(x). For example a GaAs layer can be grown onSi_(1−x)Ge_(x)-on-insulator where x is equal or close to 1. SGOI mayserve as an ultimate platform for high speed, low power electronic andoptoelectronic applications.

[0005] SGOI has been fabricated by several methods in the prior art. Inone method, the separation by implantation of oxygen (SIMOX) technologyis used to produce SGOI. High dose oxygen implant was used to bury highconcentrations of oxygen in a Si_(1−x)Ge_(x) layer, which was thenconverted into a buried oxide (BOX) layer upon annealing at hightemperature (for example, 1350° C.). See, for example, Mizuno et al.IEEE Electron Device Letters, Vol. 21, No. 5, pp. 230-232, 2000 andIshilawa et al. Applied Physics Letters, Vol. 75, No. 7, pp. 983-985,1999. One of the main drawbacks is the quality of the resultingSi_(1−x)Ge_(x) film and BOX. In addition, Ge segregation during hightemperature anneal also limits the maximum Ge composition to a lowvalue.

[0006] U.S. Pat. Nos. 5,461,243 and 5,759,898 describe a second method,in which a conventional silicon-on-insulator (SOI) substrate was used asa compliant substrate. In the process, an initially strainedSi_(1−x)Ge_(x) layer was deposited on a thin SOI substrate. Upon ananneal treatment, the strain was transferred to the thin silicon filmunderneath, resulting in relaxation of the top Si_(1−x)Ge_(x) film. Thefinal structure is relaxed-SiGe/strained-Si/insulator, which is not anideal SGOI structure. The silicon layer in the structure is unnecessary,and may complicate or undermine the performance of devices built on it.For example, it may form a parasitic back channel on this strained-Si,or may confine unwanted electrons due to the band gap offset between thestrained-Si and SiGe layer.

[0007] U.S. Pat. Nos. 5,906,951 and 6,059,895 describe the formation ofa similar SGOI structure: strained-layer(s)/relaxed-SiGe/Si/insulatorstructure. The structure was produced by wafer bonding and etch backprocess using a P⁺⁺ layer as an etch stop. The presence of the siliconlayer in the above structure may be for the purpose of facilitatingSi-insulator wafer bonding, but is unnecessary for ideal SGOIsubstrates. Again, the silicon layer may also complicate or underminethe performance of devices built on it. For example, it may form aparasitic back channel on this strained-Si, or may confine unwantedelectrons due to the band gap offset between the strained-Si and SiGelayer. Moreover, the etch stop of P⁺⁺ in the above structure is notpractical when the first graded Si_(1−y)Ge_(y) layer described in thepatents has a y value of larger than 0.2. Experiments from researchshows Si_(1−y)Ge_(y) with y larger than 0.2 is a very good etch stop forboth KOH and TMAH, as described in a published PCT application WO99/53539. Therefore, the KOH will not be able to remove the first gradedSi_(1−y)Ge_(y) layer and the second relaxed SiGe layer as described inthe patents.

[0008] Other attempts include re-crystallization of an amorphousSi_(1−x)Ge_(x) layer deposited on the top of SOI (silicon-on-insulator)substrate, which is again not an ideal SGOI substrate and the siliconlayer is unnecessary, and may complicate or undermine the performance ofdevices built on it. Note Yeo et al. IEEE Electron Device Letters, Vol.21, No. 4, pp. 161-163, 2000. The relaxation of the resultant SiGe filmand quality of the resulting structure are main concerns.

[0009] From the above, there is a need for a simple technique forrelaxed SGOI substrate production, a need for a technique for productionof high quality SGOI and other III-V material-on-insulator, and a needfor a technique for wide range of material transfer.

SUMMARY OF THE INVENTION

[0010] According to the invention, there is provided an improvedtechnique for production of wide range of high quality material isprovided. In particular, the production of relaxedSi_(1−x)Ge_(x)-on-insulator (SGOI) substrate or relaxed III-V or II-VImaterial-on-insulator, such as GaAs-on-insulator, is described. Highquality monocrystalline relaxed SiGe layer, relaxed Ge layer, or otherrelaxed 111-V material layer is grown on a silicon substrate using agraded Si_(1−x)Ge_(x) epitaxial growth technique. A thin film of thelayer is transferred into an oxidized handle wafer by wafer bonding andwafer splitting using hydrogen ion implantation. The invention makes useof the graded Si_(1−x)Ge_(x) buffer structure, resulting in a simplifiedand improved process.

[0011] The invention also provides a method allowing a wide range ofdevice materials to be integrated into the inexpensive siliconsubstrate. For example, it allows production ofSi_(1−x)Ge_(x)-on-insulator with wide range of Ge concentration, andallows production of many III-V or II-VI materials on insulator likeGaAs, AlAs, ZnSe and InGaP. The use of graded Si_(1−x)Ge_(x) buffer inthe invention allows high quality materials with limited dislocationdefects to be produced and transferred. In one example, SGOI is producedusing a SiGe structure in which a region in the graded buffer can act asa natural etch stop.

[0012] The invention provides a process and method for producingmonocrystalline semiconductor layers. In an exemplary embodiment, agraded Si_(1−x)Ge_(x) (x increases from 0 to y) is deposited on a firstsilicon substrate, followed by deposition of a relaxed Si_(1−y)Ge_(y)layer, a thin strained Si_(1−z)Ge_(z) layer and another relaxedSi_(1−y)Ge_(y) layer. Hydrogen ions are then introduced into thestrained Si_(1−z)Ge_(z) layer. The relaxed Si_(1−y)Ge_(y) layer isbonded to a second oxidized substrate. An annealing treatment splits thebonded pair at the strained Si layer, whereby the second relaxedSi_(1−y)Ge_(y) layer remains on said second substrate.

[0013] In another exemplary embodiment, a graded Si_(1−x)Ge_(x) isdeposited on a first silicon substrate, where the Ge concentration x isincreased from 0 to 1. Then a relaxed GaAs layer is deposited on therelaxed Ge buffer. As the lattice constant of GaAs is close to that ofGe, GaAs has high quality with limited dislocation defects. Hydrogenions are introduced into the relaxed GaAs layer at the selected depth.The relaxed GaAs layer is bonded to a second oxidized substrate. Anannealing treatment splits the bonded pair at the hydrogen ion richlayer, whereby the upper portion of relaxed GaAs layer remains on saidsecond substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIGS. 1A-1C are block diagrams showing the process of producing aSGOI substrate in accordance with the invention;

[0015]FIGS. 2A and 2B are infrared transmission images of an as-bondedwafer pair and a final SGOI substrate after splitting, respectively;

[0016]FIG. 3 is a TEM cross-section view of a SiGe layer that wastransferred onto the top of a buried oxide;

[0017]FIG. 4 is an AFM for a transferred SGOI substrate showing surfaceroughness; and

[0018] FIGS. 5-8 are block diagrams of various exemplary embodimentssemiconductor structures in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019] An example of a process in which SGOI is created by layertransfer is described. The experiment was performed in two stages. Inthe first stage, heteroepitaxial SiGe layers are formed by a gradedepitaxial growth technology. Starting with a 4-inch Si (100) donor wafer100, a linearly stepwise compositionally graded Si_(1−x)Ge_(x) buffer102 is deposited with CVD, by increasing Ge concentration from zero to25%. Then a 2.5 μm relaxed Si_(0.75)Ge_(0.25) cap layer 104 is depositedwith the final Ge composition, as shown in FIG. 1A.

[0020] The relaxed SiGe cap layer has high quality with very lowdislocation defect density (less than 1E6/cm²), as the graded bufferaccommodates the lattice mismatch between Si and relaxed SiGe. A thinlayer of this high quality SiGe will be transferred into the final SGOIstructure. The surface of the as-grown relaxed SiGe layer shows a highroughness around 11 nm to 15 nm due to the underlying strain fieldsgenerated by misfit dislocations at the graded layer interfaces and thuschemical-mechanical polishing (CMP) is used to smooth the surface. Inthe second stage, the donor wafer is implanted with hydrogen ion (100keV, 5E16 H⁺/cm²) to form a buried hydrogen-rich layer. After a surfaceclean step in a modified RCA solution, it is bonded to an oxidized 106Si handle wafer 108 at room temperature as shown in FIG. 1B.

[0021] The wafer bonding is one of the key steps, and the bonding energyshould be strong enough in order to sustain the subsequent layertransfer in the next step. Good bonding requires a flat surface and ahighly hydrophilic surface before bonding. On the other hand, the buriedoxide in the final bonded structure is also required to have goodelectrical properties as it will influence the final device fabricatedon it. In the conventional Si film transfer, thermal oxide on the donorwafer is commonly used before H⁺ implantation and wafer bonding, whichbecomes the buried oxide in the resulting silicon-on-insulatorstructure.

[0022] The thermal oxide of the Si donor wafer meets all therequirements, as it has good electrical properties, has flat surface andbonds very well to the handle wafer. Unlike the Si, however, theoxidation of SiGe film results in poor thermal oxide quality, and the Gesegregation during oxidation also degrades the SiGe film. Therefore thethermal oxide of SiGe is not suitable for the SGOI fabrication. In oneexemplary experiment the SiGe film will be directly bonded to anoxidized Si handle wafer. The high quality thermal oxide in the handlewafer will become the buried oxide in the final SGOI structure.

[0023] Having a flat surface after a CMP step, the SiGe wafer wentthrough a clean step.

[0024] Compared to Si, one difficulty of SiGe film is that, SiGe surfacebecomes rougher during the standard RCA clean, as the NH₄OH in RCA1solution etches Ge faster than Si. Rough surface will lead to weakbonding as the contact area is reduced when bonded to the handle wafer.In this exemplary embodiment, H₂SO₄—H₂O₂ solution is used in the placeof RCA1, which also meets the clean process requirement for thesubsequent furnace annealing after bonding. The SiGe surface afterH₂SO₄—H₂O₂ clean shows better surface roughness compared to RCA1.

[0025] After this modified clean procedure, the SiGe wafer is dipped inthe diluted HF solution to remove the old native oxide. It is thenrinsed in DI water thoroughly to make the surface hydrophilic by forminga fresh new native oxide layer that is highly active. After spinningdry, the SiGe wafer is bonded to an oxidized handle wafer at roomtemperature, and then annealed at 600° C. for 3 hours. During anneal thebonded pair split into two sheets along the buried hydrogen-rich layer,and a thin relaxed Si_(0.75)Ge_(0.25) film 110 is transferred into thehandle wafer, resulting in a SGOI substrate 112, as shown in FIG. 1B. Afinal 850° C. anneal improves the Si_(0.75)Ge_(0.25)/SiO₂ bond.Thereafter, device layers 114 can be processed on the SGOI substrate 112as shown in FIG. 1C.

[0026]FIGS. 2A and 2B are infrared transmission images of the as-bondedwafer pair and the final SGOI substrate after splitting, respectively.To investigate the surface of the as-transferred SGOI substrate,transmission electron microscopy (TEM) and atomic force microscopy (AFM)were used. The TEM cross-section view in FIG. 3 shows a ˜640 nm SiGelayer was transferred onto the top of a 550 nm buried oxide (BOX).Surface damage is also shown clearly at the splitting surface with adamage depth of ˜100 nm.

[0027]FIG. 4 shows a surface roughness of 11.3 nm in an area of 5×5 μmby AFM for the as-transferred SGOI. The data is similar to those fromas-transferred silicon film by smart-cut process, and suggests that atop layer of about 100 nm should be removed by a final CMP step. AfterSiGe film transferring, only a thin relaxed SiGe film is removed and thedonor wafer can be used again for a donor wafer. Starting from thisgeneral SGOI substrate, various device structures can be realized bygrowing one or more device layers on the top, as shown in FIG. 2C.

[0028] Electrical evaluation is in progress by growing a strain Si layeron the top of this SGOI substrate followed by fabrication of strained Sichannel devices. Bond strength is important to the process of theinvention. AFM measurements were conducted to investigate the SiGe filmsurface roughness before bonding under different conditions. Oneexperiment is designed to investigate how long the SiGe surface shouldbe polished to have smooth surface and good bond strength, since thesurface of the as-grown relaxed SiGe layer has a high roughness around11 nm to 15 nm. Several identical 4-inch Si wafers with relaxedSi_(0.75)Ge_(0.25) films were CMPed with optimized polishing conditionsfor different times. Using AFM, the measured surface mircoroughness RMSat an area of 10 μm×10 μm is 5.5 Å, 4.5 Åand 3.8 Å, for wafer CMPed for2 min., 4 min. and 6 min. respectively. After bonding to identicalhandle wafers, the tested bond strength increases with decreasing RMS. ACMP time of 6 min. is necessary for good strength.

[0029] In another experiment, two identical 4-inch Si wafers withrelaxed Si_(0.75)Ge_(0.25) films were CMPed for 8 min. After twocleaning steps in H₂SO₄:H₂O₂ solution and one step in diluted HFsolution, one wafer was put in a new H₂SO₄:H₂O₂ (3:1) solution andanother in a new NH₄OH:H₂O₂:H₂O (1:1:5), i.e. the conventional RCA1solution, both for 15 min. The resultant wafers were tested using AFM.The wafer after H₂SO₄:H₂O₂ solution shows a surface roughness RMS of 2 Åat an area of 1 μm×1 μm, which after NH₄OH:H₂O₂:H₂O shows 4.4 Å.Clearly, the conventional RCA clean roughens the SiGe surfacesignificantly, and H₂SO₄:H₂O₂ should be used for SiGe clean.

[0030] In yet another experiment, the clean procedure is optimizedbefore bonding. For direct SiGe wafer to oxidized handle wafer bonding(SiGe-oxide bonding), several different clean procedures were tested. Ithas been found that the H₂SO₄:H₂O₂ (2˜4:1) solution followed by DI waterrinse and spin dry gives good bond strength. Alternatively, one can alsodeposit an oxide layer on the SiGe wafer and then CMP the oxide layer.In this case SiGe/oxide is bonded to an oxidized handle wafer, i.e.oxide-oxide bonding. Among different clean procedures, it was found thatNH₄OH:H₂O₂:H₂O clean and DI water rinse following by diluted HF, DIwater rinse and spin dry gives very good bond strength.

[0031]FIG. 5 is a block diagram of an exemplary embodiment of asemiconductor structure 500 in accordance with the invention. A gradedSi_(1−x)Ge_(x) buffer layer 504 is grown on a silicon substrate 502,where the Ge concentration x is increased from zero to a value y in astepwise manner, and y has a selected value between 0 and 1. A secondrelaxed Si_(1−y)Ge_(y) layer 506 is then deposited, and hydrogen ionsare implanted into this layer with a selected depth by adjustingimplantation energy, forming a buried hydrogen-rich layer 508. The waferis cleaned and bonded to an oxidized handle wafer 510. An annealtreatment at 500˜600° C. splits the bonded pair at the hydrogen-richlayer 508. As a result, the upper portion of the relaxed Si_(1−y)Ge_(y)layer 506 remains on the oxidized handle wafer, forming a SGOIsubstrate. The above description also includes production ofGe-on-insulator where y=1.

[0032] During the wafer clean step prior to bonding, the standard RCAclean for the silicon surface is modified. Since the NH₄OH in standardRCA1 solution etches Ge faster than Si, the SiGe surface will becomerough, leading to a weak bond. A H₂SO₄—H₂O₂ solution is used in theplace of RCA1, which also meets the clean process requirement for thesubsequent furnace annealing after bonding. The SiGe surface after theH₂SO₄—H₂O₂ clean showed better surface roughness compared to RCA1. Afterthe modified RCA clean, the wafers are then immersed in another freshH₂SO₄—H₂O₂ solution for 10 to 20 min. H₂SO₄—H₂O₂ renders the SiGesurface hydrophilic. After a rinse in DI wafer and spin drying, the SiGewafer is bonded to an oxidized handle wafer at room temperatureimmediately, and then annealed at 500˜600° C. for wafer splitting.

[0033]FIG. 6 is a block diagram of another exemplary embodiment of asemiconductor structure 600. The structure 600 includes a gradedSi_(1−x)Ge_(x) buffer layer 604 grown on a silicon substrate 602, wherethe Ge concentration x is increased from zero to 1. Then a relaxed pureGe layer 606 and a III-V material layer 608, such as a GaAs layer, areepitaxially grown on the Ge layer. Hydrogen ions are implanted into theGaAs layer 608 with a selected depth by adjusting implantation energy,forming a buried hydrogen-rich layer 610. The wafer is cleaned andbonded to an oxidized handle wafer 612. An anneal treatment splits thebonded pair at the hydrogen-rich layer 610. As a result, the upperportion of the GaAs layer 608 remains on the oxidized handle wafer,forming a GaAs-on-insulator substrate.

[0034]FIG. 7. is a block diagram of yet another exemplary embodiment ofa semiconductor structure 700. A graded Si_(1−x)Ge_(x) buffer layer 704is grown on a silicon substrate 702, where the Ge concentration x isincreased from zero to a selected value y, where y is less than 0.2. Asecond relaxed Si_(1−z)Ge_(z) layer 706 is deposited, where z is between0.2 to 0.25. Hydrogen ions are implanted into the graded Si_(1−x)Ge_(x)buffer layer 704 with a selected depth, forming a buried hydrogen-richlayer 708 within layer 704. The wafer is cleaned and bonded to anoxidized handle wafer 710. An anneal treatment at 500˜600° C. splits thebonded pair at the hydrogen-rich layer 708.

[0035] As a result, the upper portion of the graded Si_(1−x)Ge_(x)buffer layer 704 and the relaxed Si_(1−z)Ge_(z) layer 706 remains on theoxidized handle wafer 710. The remaining graded Si_(1−x)Ge_(x) bufferlayer 704 is then selectively etched by either KOH or TMAH. KOH and TMAHetch Si_(1−x)Ge_(x) fast when x is less 0.2, but becomes very slow whenx is larger than 0.2. Thus, the graded Si_(1−x)Ge_(x) buffer layer 704can be etched selectively, leaving the relaxed Si_(1−z)Ge_(z) layer 706on the insulating substrate 710 and forming a relaxed SGOI substrate. Inthis process, the thickness of the relaxed Si_(1−z)Ge_(z) film 706 onthe final SGOI structure is defined by film growth, which is desired insome applications.

[0036]FIG. 8 is a block diagram of yet another exemplary embodiment of asemiconductor structure 800. A graded Si_(1−x)Ge_(x) buffer layer 804 isgrown on a silicon substrate 802, where the Ge concentration x isincreased from zero to a selected value y between 0 and 1. A secondrelaxed Si_(1−y)Ge_(y) layer 806 is deposited, followed by a strainedSi_(1−z)Ge_(z) layer 808 and another relaxed Si_(1−y)Ge_(y) layer 810.The thickness of layers 806, 808, and 810, and the value z are chosensuch that the Si_(1−z)Ge_(z) layer 808 is under equilibrium strain statewhile the Si_(1−y)Ge_(y) layers 806 and 810 remain relaxed. In oneoption, hydrogen ions may be introduced into the strained Si_(1−z)Ge_(z)layer 808, forming a hydrogen-rich layer 812. The wafer is cleaned andbonded to an oxidized handle wafer 814. The bonded pair is thenseparated along the strained Si_(1−z)Ge_(z) layer 808.

[0037] Since the strain makes the layer weaker, the crack propagatesalong this layer during separation. The separation can be accomplishedby a variety of techniques, for example using a mechanical force or ananneal treatment at 500˜600° C. when the hydrogen is also introduced.See, for example, U.S. Pat. Nos. 6,033,974 and 6,184,111, both of whichare incorporated herein by reference. As a result, the relaxedSi_(1−y)Ge_(y) layer 810 remains on the oxidized handle wafer, forming arelaxed SGOI substrate. The thickness of layers 806, 808, and 810, andthe value z may also be chosen such that there are a good amount ofdislocations present in the Si_(1−z)Ge_(z) layer 808 while the topSi_(1−y)Ge_(y) layer 810 remains relaxed and having high quality andlimited dislocation defects.

[0038] These dislocation defects in the Si_(1−z)Ge_(z) layer 808 canthen act as hydrogen trap centers during the subsequent step ofintroducing ions. The hydrogen ions may be introduced by various ways,such as ion implantation or ion diffusion or drift by means ofelectrolytic charging. The value of z may be chosen in such a way thatthe remaining Si_(1−z)Ge_(z) layer 808 can be etched selectively by KOHor TMAH. The layers 806 and 810 may also be some other materials, forexample pure Ge, or some III-V materials, under the condition that theGe concentration x in the graded Si_(1−x)Ge_(x) buffer layer 804 isincreased from zero to 1.

[0039] After all the semiconductor-on-insulator substrate obtained bythe approaches described above, various device layers can be furthergrown on the top. Before the regrowth, CMP maybe used to polish thesurface.

[0040] Although the present invention has been shown and described withrespect to several preferred embodiments thereof, various changes,omissions and additions to the form and detail thereof, may be madetherein, without departing from the spirit and scope of the invention.

What is claimed is:
 1. A process of forming a semiconductor structurewith a relaxed Si_(1−y)Ge_(y) layer, comprising: depositing a gradedSi_(1−x)Ge_(x) buffer layer on a first substrate, wherein said Geconcentration x is increased from zero to a value y; depositing arelaxed Si_(1−y)Ge_(y) layer; introducing ions into said relaxedSi_(1−y)Ge_(y) layer to define a first heterostructure; bonding saidfirst heterostructure to a second substrate to define a secondheterostructure; splitting said second heterostructure in the region ofthe introduced ions, wherein a top portion of said relaxedSi_(1−y)Ge_(y) layer remains on said second substrate.
 2. The process ofclaim 1 further comprising forming at least one device layer or aplurality of integrated circuit devices, after said step of depositingsaid relaxed Si_(1−y)Ge_(y) layer.
 3. The process of claim 2, whereinsaid at least one device layer comprises at least one of strained Si,strained Si_(1−w)Ge_(w) with w≠y, strained Ge, GaAs, AlAs, ZnSe andInGaP.
 4. The process of claim 1 further comprising forming aninsulating layer before said step of introducing ions.
 5. The process ofclaim 1 further comprising planarizing said relaxed Si_(1−y)Ge_(y)layer, before said step of introducing ions.
 6. The process of claim 1,wherein said ions comprise hydrogen H⁺ ions or H₂ ⁺ ions.
 7. The processof claim 1 further comprising planarizing said relaxed Si_(1−y)Ge_(y)layer, after said step of introducing ions.
 8. The process of claim 1further comprising cleaning both said first heterostructure and saidsecond substrate, before said step of bonding.
 9. The process of claim1, wherein said second heterostructure is split by annealing.
 10. Theprocess of claim 1, wherein said second heterostructure is split byannealing followed by mechanical force.
 11. The process of claim 1further comprising removing the top portion of the remaining of saidrelaxed Si_(1−y)Ge_(y) layer, after said step of splitting.
 12. Theprocess of claim 1 further comprising forming at least one device layer,or a plurality of integrated circuit devices, after said step ofsplitting.
 13. The process of claim 12, wherein said at least one devicelayer comprises at least one of relaxed Si_(1−y)Ge_(y), strained Si,strained Si_(1−w)Ge_(w), strained Ge, GaAs, AlAs, ZnSe and InGaP. 14.The process of claim 1 further comprising re-using the remaining firstheterostructure, after said step of splitting.
 15. The process of claim1, wherein said first substrate comprises monocrystalline silicon.
 16. Aprocess of forming a semiconductor layer, comprising: depositing agraded Si_(1−x)Ge_(x) buffer layer on a first substrate, said Geconcentration x being increased from zero to 1; depositing a relaxed Gelayer; forming a monocrystalline semiconductor layer including anothermaterial whose lattice constant is approximately close to that of Ge;introducing ions into said semiconductor layer to define a firstheterostructure; bonding said first heterostructure to a secondsubstrate to define a second heterostructure; splitting said secondheterostructure in the region of introduced ions, wherein a top portionof said semiconductor layer remains on said second substrate.
 17. Theprocess of claim 16, wherein said semiconductor layer comprises one ofGaAs, AlAs, ZnSe and InGaP.
 18. The process of claim 16 furthercomprising forming at least one device layer or a plurality ofintegrated circuit devices, after said step of forming saidsemiconductor layer.
 19. The process of claim 16 further comprisingforming an insulating layer before said step of introducing ions. 20.The process of claim 16 further comprising planarizing saidsemiconductor layer before said step of introducing ions.
 21. Theprocess of claim 16, wherein said ions comprise hydrogen H⁺ ions or H₂ ⁺ions.
 22. The process of claim 16, further comprising the step ofplanarizing said semiconductor layer after said step of introducingions.
 23. The process of claim 16 further comprising cleaning both saidfirst heterostructure and said second substrate, before said step ofbonding.
 24. The process of claim 16, wherein said secondheterostructure is split by annealing.
 25. The process of claim 16,wherein said second heterostructure is split by annealing and followedby mechanical force.
 26. The process of claim 16 further comprisingremoving the top portion of the remaining of said third semiconductorlayer, after said step of splitting.
 27. The process of claim 16 furthercomprising forming at least one device layer or a plurality ofintegrated circuit devices, after said step of splitting.
 28. Theprocess of claim 16 further comprising re-using the remaining firstheterostructure, after said step of splitting.
 29. The process of claim16, wherein said first substrate comprises monocrystalline silicon. 30.A process of forming a semiconductor structure with a relaxedSi_(1−z)Ge_(z) layer, comprising: depositing a graded Si_(1−x)Ge_(x)buffer layer on a first substrate, said Ge concentration x beingincreased from zero to a selected value y, and y being less than 0.2;depositing a relaxed Si_(1−z)Ge_(z) layer, where z is between 0.2 and0.25; introducing ions into said graded Si_(1−x)Ge_(x) buffer layer todefine a first heterostructure; bonding said first heterostructure to asecond substrate to define a second heterostructure; splitting saidsecond heterostructure in the region of introduced ions, wherein theupper portion of first graded Si_(1−x)Ge_(x) layer and said relaxedSi_(1−z)Ge_(z) layer remains on said second substrate; and selectivelyetching the remaining portion of said graded Si_(1−x)Ge_(x) layer,wherein said relaxed Si_(1−z)Ge_(z) layer remains on said secondsubstrate.
 31. The process of claim 30 further comprising forming atleast one device layer or a plurality of integrated circuit devices,after said step of forming said relaxed Si_(1−z)Ge_(z) layer.
 32. Theprocess of claim 31, wherein said at least one device layer includes oneor more of strained Si, strained Si_(1−w)Ge_(w) with w≠z, and strainedGe.
 33. The process of claim 30 further comprising forming an insulatinglayer before said step of introducing ions.
 34. The process of claim 30further comprising planarizing said relaxed Si_(1−z)Ge_(z) layer beforesaid step of introducing ions.
 35. The process of claim 30, wherein saidions comprise hydrogen H⁺ ions or H₂ ⁺ ions.
 36. The process of claim 30further comprising planarizing the relaxed Si_(1−z)Ge_(z) layer aftersaid step of introducing ions.
 37. The process of claim 30 furthercomprising cleaning both said first heterostructure and said secondsubstrate, before said step of bonding.
 38. The process of claim 30,wherein said second heterostructure is split by annealing.
 39. Theprocess of claim 30 further comprising planarizing said second relaxedSi_(1−z)Ge_(z) layer after said step of etching.
 40. The process ofclaim 30 further comprising forming at least one device layer or aplurality of integrated circuit devices, after said step of etching. 41.A process of forming a semiconductor layer, comprising: depositing agraded Si_(1−x)Ge_(x) buffer layer on a first substrate, said Geconcentration x being increased from zero to a value y; depositing arelaxed Si_(1−y)Ge_(y) layer; depositing a strained or defect layer;depositing a relaxed layer; introducing ions into said strained ordefect layer to define a first heterostructure; bonding said firstheterostructure to a second substrate to define a secondheterostructure; and splitting said second heterostructure in the regionof the strained or defect layer, wherein said relaxed layer remains onsaid second substrate.
 42. The process of claim 41, wherein saidstrained or defect layer comprises either a strained Si_(1−z)Ge_(z)layer with z≠y, or other III-V material.
 43. The process of claim 41,wherein said relaxed layer or said strained or defect layer compriseseither a relaxed Si_(1−w)Ge_(w) layer where w is close or equal to y,or, when y is equal to 1, one of Ge, GaAs, AlAs, ZnSe and InGaP.
 44. Theprocess of claim 41 further comprising forming at least one device layeror a plurality of integrated circuit devices, after said step ofdepositing said relaxed layer.
 45. The process of claim 41 furthercomprising forming an insulating layer before said step of introducingions.
 46. The process of claim 41 further comprising planarizing saidrelaxed layer before said step of introducing ions.
 47. The process ofclaim 41, wherein said ions comprise hydrogen H⁺ ions or H₂ ⁺ ions. 48.The process of claim 41 further comprising planarizing said relaxedlayer after said step of introducing ions.
 49. The process of claim 41further comprising cleaning both said first heterostructure and saidsecond substrate, before said step of bonding.
 50. The process of claim41, wherein said second heterostructure is split by annealing.
 51. Theprocess of claim 41 further comprising removing one of any remaining ofsaid strained or defect layer, and the top portion of said relaxedlayer, after said step of splitting.
 52. The process of claim 41 furthercomprising forming at least one device layer or a plurality ofintegrated circuit devices, after said step of splitting.
 53. Theprocess of claim 41 further comprising re-using the remaining firstheterostructure for a subsequent process after planarizing.
 54. Asemiconductor structure comprising: a first semiconductor substrate; asecond layer of relaxed Si_(1−x)Ge_(x), wherein x=0.1 to 1; and a thirdlayer comprising at least one of GaAs. AlAs, ZnSe and InGaP, or strainedSi_(1−y)Ge_(y) wherein y≠x.
 55. A semiconductor structure comprising: afirst substrate comprising monocrystalline silicon substrate; a secondlayer of graded Si_(1−x)Ge_(x) buffer layer, wherein said Geconcentration x is increased from zero to a value y; a third layer ofrelaxed Si_(1−y)Ge_(y); a fourth strained or defect layer comprisingeither a strained Si_(1−z)Ge_(z) layer with z≠y, or other III-V or II-VImaterial; and a fifth relaxed layer comprising either a relaxedSi_(1−w)Ge_(w) layer where w is close or equal to y, or, when y is equalto 1, at least one of Ge, GaAs, AlAs, ZnSe and InGaP.